The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advancements to be realized, similar developments in IC processing and manufacturing are needed.
For example, in FINFET fabrication processes, it is typical to recess the fins in their source/drain (S/D) regions and to epitaxially grow some semiconductor materials over the recessed fins as S/D features. Such a method sometimes introduces the following problems. First, the recess of the fins may introduce variations in the recess profile due to etch loading effects among other factors. The variations in the recess profile sometimes lead to variations in the epitaxial S/D features. Second, the recess of the fins may sometimes lead to the relaxation of the strains built into the channel region of the fins. Accordingly, improvements in the FINFET S/D engineering are desirable.